What the hardware holds
Today's memory hierarchy knows addresses and pages. A page has no identity, no history and no lifecycle, so nothing in the machine can reason about the conversation living inside it.
SCMA places a table inside the memory controller with one row per live session. That row is what makes every other behaviour possible: because the hardware can name a session, it can time it, move it, transform it, account for it and audit it.
Four states, advanced by the hardware
Each session descends as it falls silent and returns when needed. The controller does this alone; the host is never consulted.
Demotes on silence
A residency timer counts up while nothing touches the session. Past a threshold the controller moves it down a tier and records that it did.
Transforms on the way down
The same pass that moves the bytes reduces their precision and encrypts them under a key belonging to that session.
Meters the durable tier
Flash has finite write endurance. An admission structure meters migrations against a replenishing budget and diverts denied transitions rather than discarding state.
Keeps a verifiable record
Every transition appends a hash-chained entry, so a session's residency history can be replayed and independently checked.
Compute where the session sleeps
Conventional accelerators pull state toward arithmetic. At the bandwidths agentic inference needs, that traffic is the cost.
SCMA's active tier is memory with arithmetic beside the banks, so attention runs inside the device holding the session. The internal bandwidth next to a memory array far exceeds anything the external interface can carry, and that ratio exists only in memory built with cheap interfaces.
The honest question is never the ratio on paper. It is what survives thermal limits, refresh, row activation, command serialisation and allocation imbalance. We model all of it.