| Question put to the model | Result | Reading |
|---|---|---|
| Does computing inside memory pay, after real losses? Effective bandwidth after thermal, refresh, row-activation, command-serialisation and allocation losses | standard part 6.40 → 3.11 co-designed 9.60 → 6.10 | A standard part does not clear the bar A co-designed bank does |
| Can a sleeping session wake inside the objective? 500 simultaneous wake-ups, 10 ms objective | full restore p99 34.1 / 121.7 ms index-first p99 0.22 ms | Objective met on every modelled wake |
| Does the lifecycle hold under sustained load? 12,000 sessions per second, 88,000 resident | wake p99 1.1 ms 0 dropped prefetch hit rate 100% | Holds in the modelled scenario |
| Do agents genuinely reuse their context? Real production trace, 7,182 sessions | 87.9% token-weighted prefix reuse | Observed in real data |
| Does sleeping wear out the durable tier? Write-endurance replay | ungoverned demand exceeds budget 6–71× | Requires an admission governor |
Eight on paper, three delivered
In August 2026 a major memory manufacturer published its own processing-in-memory part. Its figures show roughly eight times the internal bandwidth of the ordinary interface, delivering an end-to-end inference speedup of about three times.
That gap is the same loss waterfall shown here, measured by an independent party, on real silicon. We treat it as the most useful external confirmation available that the honest question is effective bandwidth.
It is also the clearest statement of where the difficulty in this company lies: in a co-designed memory bank, not in a simulator.
How a result earns its place
A figure enters a document only when a committed model reproduces it. Comparisons credit any optimisation available to a competing system to that system first. Constants that are placeholders are labelled as placeholders everywhere they appear, and results that stop regenerating are retired.
What these results do not prove
- The co-designed bank is a target, not a part. No shipped silicon demonstrates it.
- Timing constants are stand-ins from an earlier generation, pending real device data.
- Simulation validates questions, not products. None of this measures hardware.
- Memory pricing is carried as scenarios with bands; on present pricing the economics do not close.
- Trace coverage is strong for tool agents and thinner for long-context coding agents.
- Freedom to operate in processing-in-memory involves substantial third-party rights.